a) Field of the Invention
The present invention relates to a semiconductor device having multi-level wirings and a method of manufacturing the same, and more particularly to a technique of forming multi-layer wirings using refractory metal as a lower level wiring.
b) Description of the Related Art
In a conventional semiconductor device, Al or Al alloy has been mainly used as a stack or layered wiring. Used as a laminate wiring are, for example, an Al/TiN/Ti stack structure having an Al layer and an TiN layer on a Ti layer in this order from the top and an Al/TiN stack structure having an Al layer on the TiN layer. An Al/TiN/Ti stack structure has been generally used particularly for a lower level wiring. In this specification, A/B means that an A layer is stacked upon a B layer.
As semiconductor devices are miniaturized more and more, a wiring width, a contact hole diameter, and the like have become smaller particularly at a lower level wiring. As the pattern size becomes fine, a density of current flowing through an Al wiring increases and electromigration in the Al wiring is likely to cause a resistance increase and a wiring open failure. There is therefore some fear of lowered reliability of semiconductor devices.
Degraded performance such as low endurance or resistance to stress migration caused by fine patterns have also increased reliability concerns.
In order to solve the above problems, attention has been paid to a technique of using refractory metal tungsten (W) instead of Al as a lower level wiring.
FIG. 8 is a cross sectional view of a substrate with a multi-level wiring structure having a similar structure to a conventional Al multi-level wiring structure and using an W layer as a lower level wiring. On a silicon substrate 50, a boro-phospho-silicate glass (BPSG) film 51 is formed. A Ti film 52, a TiN film 53, and a W film 54 are deposited on a predetermined surface area of the BPSG film 51 in this order from the bottom to form a lower level wiring. The lower level wiring is electrically connected to a silicon substrate 50 or a polycrystalline silicon electrode at a contact region (not shown) through a contact hole formed in the BPSG film 51.
An inter-level insulating film 55 is formed on the lower level wiring and the BPSG film 51. A connection or via hole is formed in the inter-level insulating film 55 for electrical connection to the lower level wiring. An upper level wiring of a stack or laminate structure having a Ti layer 56 and an Al alloy layer 57 thereon is formed on the inter-level insulating film 55. The upper level wiring is electrically connected to the lower level wiring through the connection hole formed in the inter-level insulating layer 55.
With the multi-level wiring structure shown in FIG. 8, contact resistance between the Al alloy layer 57 and W layer 54 increases because of heating during the formation of a passivation film after forming the upper level wiring or because of heating during annealing.